3724 Winter 2014 Assignment 3 Due Date: 25th February 9am 1. Creating Digital Circuits: The Half-Adder a) implement the AND operation as a circuit using only 2 NAND gates [5 marks] b) check your design in (a) by showing the full truth table for it [5 marks] (demonstrate that F=1 when x=1, y=1, otherwise 0) c) implement the OR operation as a circuit using only 3 NAND gates [5 marks] d) check your design in (c) by showing the full truth table for it [5 marks] (demonstrate that F=0 when x=0, y=0, otherwise 1) e) by observing that x⊕y = (x+y).(x̅.̅y̅), implement the XOR operation as a circuit using at most 6 NAND gates [5 marks] f) check your design in (e) by showing the full truth table for it [5 marks] (demonstrate that F=1 when x=1, y=0 or when x=0, y=1, otherwise 0) 2. Analysing Circuits: The Better-Half-Adder. Complete a truth table... and hence show that this half adder functions correctly [10 marks] A B 1 2 3 S C 0 0 1 1 1 0 0 0 1 1 1 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 1 And we see that s = A XOR B and that C = A.B as required for an half-adder. 3. Karnaugh Maps. For each function create a Kmap and hence simplify: a) F(x,y,z) = x̅.y̅.z + x̅.y.z + x̅.y.z̅ + x.y̅.z̅ [10 marks] yz x 00 01 11 10 0 0 1 1 1 1 1 0 0 0 Simplified Function: follow x̅ & y, ignore z OR follow x̅ & z, ignore y OR when x & y̅ & z̅ " " " " " " " " = x̅.y + x̅.z + x.y̅.z̅ b) F(x,y,z) = x̅.y̅.z + x̅.y.z + x.y̅.z̅ + x.y.z̅ [10 marks] yz x 00 01 11 10 0 0 1 1 0 1 1 0 0 1 Simplified Function: follow x̅ & z, ignore y OR follow x & z̅, ignore y " " " " " " " " " " = x̅.z + x.z̅ (which you may notice" = x ⊕ z ) c) F(w,x,y,z) = y̅.z + w.y̅ + w̅.x.y + w̅.x̅.y.z̅ + w.x̅.y.z̅ [15 marks] yz wx 00 01 11 10 00 0 1 0 1 01 0 1 1 1 11 1 1 0 0 10 1 1 0 1 Simplified Function: follow w̅ & x̅ & y, ignore z OR follow y̅ and z, ignore w & x OR follow x̅ & y & z̅, ignore w OR follow w & y̅, ignore x & z " " " " " " " " = w̅.x.y + y̅.z + x̅.y.z̅ + w.y̅ 4. Sequential Circuits. By tracing what happens carefully, show the new states of B0, B1, B2, B3, and the outputs at A, B, C and the Output Carry. [15 marks] You can trace this with a table, with one row per event, or describe the events in chronological order as I have done here. It is important to note that only the inputs to the JK Flip-Flops are timed by the clock. Look closely and you’ll see that All the other circuitry is ‘live’ throughout, including the outputs B0, B1, B2, B3 from the flip-flops. So, crucially, before the clock pulses the outputs from count enable, B0, B1, B2, B3 are all 1, as therefore so are the outputs from the AND gates at A, B, C, and from the AND gate at Output Carry (look at your diagram and you can see this now). Therefore the prospective inputs to every JK Flip-Flop are ‘1-1’ too (J=1 & K=1). So all the JK-Flip-Flops are just waiting to be fed an input of ‘1-1’ the very instant that the clock pulses. And when it does pulse, the ‘1-1’ input causes them all to flip their outputs to 0. Then, and only then, the impact of the changed outputs at B0, B1, B2, B3 begins to cascade through the circuit: -the outputs of each of A, B and C become 0 (respectively: 1.0 = 0, 0.0 = 0, 0.0 = 0) -the flip flops at B1, B2, B3 now take input of J=0, K=0, which leaves their outputs the same (B0, B1, B2, B3 all remain 0) -so the Output Carry takes input of C=0, B3=0, giving 0.0 = 0 as the final Output Carry value. So, overall the counter gets reset to 0000, while the value read on the output carry will depend upon when it is read: if it is read just before or at the very moment that the clock is pulsed, it will be ‘1’; if it is read very shortly afterwards, when all the changes have cascaded through the circuit, then it will be ‘0’, as if the counter circuit was new and had never been used! Please make sure that you can follow this argument and see me if you are still not clear.

© Copyright 2018 ExploreDoc