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Middle-East Journal of Scientific Research 20 (12): 2252-2257, 2014
ISSN 1990-9233
© IDOSI Publications, 2014
DOI: 10.5829/idosi.mejsr.2014.20.12.315
A Novel Low Power CMOS PLL for Clock Generation
A. Geetha
Department of ETE,
Bharath Univeristy, India
Abstract: In this paper we propose a Low Power Phase Locked Loop (PLL) using transmission gate logic (TG).
The proposed PLL has a simpler structure using very less number of transistors compared to the conventional
PLL and results in better performance than any other published PLL’s due to no DC leakage currents and
reduced transistor count. The PLL has a dead zone less than 0.01ns in the phase characteristics and has low
phase sensitivity errors. The PLL is independent from the duty cycle of input signals and the effects of clock
feed – through are reduced by separating the output stage from UP and DOWN signal. The PLL is designed
using 0.8 µm CMOS technology. We compared the proposed PLL with the conventional PLL with respect to
performance and power consumption. The Results show 30% reduction in power consumption over a
conventional PLL with comparable performance.
Key words: Low Power
Phase and Frequency Detector
The minimum channel length of the transistor will
be scaled down to 0.065 um in 2007, according to the
roadmap of semiconductors. In addition to this
downscaling, today’s system-on-chip (SoC) trend forces
analog and digital integrated circuits (ICs) to be integrated
on a single chip called the complete SoC. At present, there
are many demands on the complete SoC in wireless and
broadband communications – wireless networking
(WLAN, voice/data communication and Bluetooth), wired
communication (WAN and LAN) and consumer
electronics (DVD, MP3, digital cameras, video games
and so on). Therefore, as one of the mixed-signal Ics,
Phase-Locked Loop (PLL) must follow this complete SoC
trend. This chapter introduces the challenges in designing
PLL and possible solid-state technologies for the
complete SoC trend.
The Low Power phase locked loop (PLL) circuit is
used to synchronize an output signal, which is usually
generated by an oscillator, with a reference or input signal
in Frequency as well as in phase. In the synchronized
state, the difference (error) between the reference and the
oscillator output is zero or at least very small. So it is
called ‘locked’. The whole circuit consists of three main
parts. They are phase & frequency detector (PFD), charge
Pump, loop filter (LP) voltage control oscillator (VCO) and
divider. The diagram of the PLL is shown in Figure 1.
Mixed signal circuits
The main motivation for this paper is to design a PLL
that will allow on-chip direct digitization of a wideband RF
signal. Yet one of the major challenges in developing the
complete SoC product for the wireless digital network
market is the integration of radio frequency (RF) analog
circuit devices, which are mostly passive discrete devices.
Eventually, we want to replace the passive devices with
active devices. We also want to replace analog designs
with full-digital implementations. To do this, a suitable
PLLs architecture, concentrating on low jitter and power,
for the complete SoC should be devised.
In section II, the proposed Novel Low Power Phase
Locked Loop is described. The results of proposed PLL
circuit are presented and comparisons are made in section
III. In section IV, draws a conclusion.
Design of Novel Low Power PLL: This section provides
detailed information about the proposed PLL, including its
major components. Also important characteristics of the
PLL are introduced for simulation and analysis, which will
be described in this section.
Phase and Frequency Detector: The input phase errors
are detected by Phase and Frequency Detector (PFD).
These phase or frequency errors are converted into
current or voltage to control the output frequency of
Voltage Controlled Oscillator (VCO) by charge pump in a
charge pump PLL. PFD detects a phase error between the
Corresponding Author: A. Geetha, Department of ETE, Bharath Univeristy, India.
Middle-East J. Sci. Res., 20 (12): 2252-2257, 2014
Fig. 1: Low Power PLL
Fig. 2: Conventional PFD Schematic
reference signal and the output signal of PLL and the error
detection range can be extended with PFD. A
conventional CMOS PFD [1-4] is shown in Fig. 2 has large
dead zone in phase characteristics at the steady state
which generates a large jitter in clocked state in PLL and
consumes large amount of power, which cannot be
avoided in high frequency operations because internal
nodes of PFD are not completely pull up or pull down.
The additional prescaler circuits can be added to lower the
frequency of the input signals. However, as the division
ratio increases, the steady state phase error will increase.
The capture range of PLL is determined by the error
detection range of PFD. A conventional CMOS PFD has
no limit to the error detection range. Therefore, the
capture range of PLL is only limited by the Voltage
Controlled Oscillator (VCO) output frequency range [5].
Our novel PFD uses a two multiplexers, as the phase
difference between the input decreases, the pulse width
on UP or DOWN also decreases. These simultaneous up
and down signals in the steady state of the PLL create a
short circuit in the charge pump which results in a
perturbation on LF voltage and produce jitter. To limit the
LF voltage perturbation without having a dead zone, we
have reduced the minimum UP and DOWN pulse widths
by reducing the reset delay in the PFD.Moreover, the
linearity of the PFD is affected by this minimum pulse
width on UP and DOWN when there is no phase
difference between the inputs of the PFD.The new PFD
has no dead zone and the nonlinearity near the steady
state of the PLL is reduced. This implementation also
reduces the transistor count to a large extent.
The conventional phase and frequency detector
(PFD) uses a two D-flip-flop (DFF) structure shown
Fig. (1). The DFF has been simplified and implemented
using a two 2:1 multiplexer as shown Fig. (4), is optimized
to obtain a minimum PFD delay with reduced power
consumption. This new PFD schematic has a reduced
delay because the number of serial MOS devices in each
gate is limited. The new PFD results in a reduced dead
zone and non-linearity near the steady state of the PLL.
The conventional PFD has the same basic function as
the NAND based PFD, but the state assignment is
different. Two D flip flops with D=1 are clocked with the
clock signals which are compared. If CLK is active before
VCO the UP output is generated while DOWN is
produced if VCO is active before CLK. As soon as the two
clock signals are simultaneously active at the same time,
ideally neither up or down has to be set. In such case, the
reset signal R has to be fast enough to minimize the UP
and DOWN activation time when PLL is in the steady
state (perfect synchronization between CLK and VCO).
Each DFF used in the conventional PFD uses 19
MOS transistors shown in Fig. 3 Based on this DFF,
Fig. 4 shows the PFD according to Fig. 3 depicted uses 42
MOS transistors, the reset signal R is controlled by NQ.
In the design of our novel PFD the 2:1 multiplexer
replaces the each DFF of Fig. 3, shown in Fig. 5. The PFD
using two 2:1 multiplexer uses 9 MOS transistors. The
Multiplexers are designed using transmission gate.
The design of the new PFD has been performed using an
asynchronous race free design method. A detailed
description of this design methodology is presented in
Middle-East J. Sci. Res., 20 (12): 2252-2257, 2014
Fig. 3: DFF Using 19 MOS Transistors
Fig. 4: Phase And Frequency Detector
Fig. 5: Novel PFD Using Multiplexer
Middle-East J. Sci. Res., 20 (12): 2252-2257, 2014
[5] and [6]. A basic schematic of such a circuit is shown
in Fig. 5. This circuit has the same basic function as the
conventional based PFD.In conventional PFD two D flip
flops with D=1 are clocked with the clock signals which
are compared. If CLK is active before VCO the UP output
is generated while DOWN is produced if VCO is active
before CLK. As soon as the two clock signals are
simultaneously active at the same time, ideally neither up
or down has to be set and a reset signal is given to the
DFF and the system is locked as there is perfect
synchronization between CLK and VCO [7-11].
The architecture of our novel PFD has one three
input NAND gate and two 2:1 multiplexers. One of the
input of the NAND gate is always made high and the
other input are UP and DOWN signals. The selection
input of multiplexer (1) is CLK and of multiplexer (2) is
output of VCO. The output of the NAND gate is given to
the input i0 of both the multiplexers and the input i1 of the
both the multiplexer are grounded.
The operation of the our novel PFD, if CLK is active
before VCO the UP output is generated because the CLK
given to selection input of the Multiplexer (1) is activated
before VCO and the UP value is high so the reset value is
low which in turn makes the input to be same. while
DOWN is produced if VCO is active before CLK because
the VCO given to selection input of the Multiplexer (2) is
activated before CLK. As soon as the two clock signals
are simultaneously active at the same time, ideally neither
UP or DOWN has to be set. In such case, the reset signal
R is given to the NAND gate becomes high and therefore
the output value changes to low which depicts the reset
state of DFF. This results in lower jitter and better linearity
near steady state without dead zone and reduced power
consumption [12].
Charge Pump: A charge pump consists of two switched
current sources that pump charge into or out of the loop
filter according to two logical inputs. The circuit has three
states. Charge pump consists of two PMOS and two
NMOS, which are connected serially. Both of the NMOS
are in the pull down section and both of the PMOS are in
the pull up section. The gate of uppermost PMOS is
connected to GND The gate of lowermost NMOS is
connected to VDD. The gates of the remaining NMOS and
PMOS are connected to the "Down" and "Up" pin of the
output of PFD. The width of the uppermost PMOS is
15 um and the length of it is 7.5 um. The width of the other
PMOS is 30 um and length of it is 600 nm. The width of
the lowermost NMOS is 7.5 um and length of it is also
7.5 um. The width of the other NMOS is 15 um and the
length of it is 600 nm.
Table 2: Calculated Power At 120 Mhz @1.35V
Total number of Transistors
Power consumption
Novel PFD using
Table 1: Calculated Area (With Parasitic Coupling Capacitance Extracted
From Layout) The Output Peak To Peak Jitter At120mhz @1.35V
Conventional PFD
Dead Zone (Jitter)
Layout Area (mm2)
< 10ps
Novel PFD using MUX
< 8ps
Fig. 6: Charge Pump
Low Pass Filter: The Filter used here is a simple low
pass Filter. It is comprised of a capacitor and a resistor.
The resistor value is 300 k ohm and capacitor is 10 pico
farad. The control voltage for the VCO is taken parallel to
the capacitor. The values of the component here are taken
iteratively. Basically these values allow control voltage to
be stable so that small changes or interferences do not
affect the locked stage [13].
Voltage Controlled Oscillator: As far as the PSNR and
low-supply voltage operation are concerned, the VCO is
the most critical block because its internal noise results
directly in jitter. Moreover, low-voltage operation limits
the design options. To obtain a fully integrated PLL, a
current-controlled ring oscillator (CCO) is the basic
element of the VCO. It allows low-voltage operation, since
no additional capacitances have been used on internal
nodes other than the ones created by the inverter devices.
To limit the MOS device channel white noise, the current
Middle-East J. Sci. Res., 20 (12): 2252-2257, 2014
Fig. 8: Output of Phase Locked Loop during the locked condition of input and VCO signal.
flowing in the CCO must be efficiently high [14]. Allowing
a limited amount of white noise in the CCO and given an
operating frequency, it can be shown that the voltage
across the CCO is minimum and depends only on process
parameters which are the best case for a given process.
Then as the supply voltage is specified, the maximum
saturation voltage of the mirror supplying the current to
the CCO is determined. Working down to 1.2V, it is not
possible to use a cascoded mirror because the saturation
voltage of such a mirror is too high for the expected
PSNR. Therefore, to ensure a maximum PSNR even at
low-supply voltages, a new circuit called active cascode
has been used.
The high-frequency PSNR is mainly determined by
the ratio of the parasitic capacitance of the mirror MOS
devices and the filtering capacitor across the CCO.
This last capacitor cannot be increased too much because
it introduces a pole in the PLL that can make it unstable.
The size of the mirror devices is determined by the
maximum allowable saturation voltage. The stability of
this active cascode is ensured by the resistor R between
the input and output of the mirror. The relation between
current and frequency in this CCO is not linear. To a first
approximation, the frequency depends on the square root
of the current for a voltage across the CCO much larger
than the maximum threshold voltage of PMOS or NMOS
devices. To obtain a linear gain for the VCO, the voltage
to current converter should have a quadratic transfer
function. This is achieved by using a MOS device in
strong inversion [15].
Divider: Frequency Divider divides the output frequency
before feeding it to PFD. It takes input from VCO and
divides the frequency, which is the dclock signal. The
Frequency Divider designed for the PFD DPLL is
programmable. It takes 8 bit input to divide the frequency
so the frequency can be divided by 1 to 255 times. The
Frequency Divider has three basic parts - an 8-bit
synchronous counter, an array of 2input XNOR gates to
take input bits and an 8 input Nand gate. The schematic
of the Frequency Divider is shown in the Figure 3.6. The
Jitter introduced by these dividers is cancelled by a D Flip
flop that resynchronizes the output signal of the dividers
with the output frequency of the PLL.The divider is
implemented using transmission gate, therefore there is
drastic reduction in the transistor count.
Verifications for logic, timing simulations are done by
using Modelsim, power estimations and final layout
without any DRC and LVS problems using Microwind is
also shown in Fig. 9.
Fig. 9: Layout Of Low Power CMOS Phase Locked Loop
Middle-East J. Sci. Res., 20 (12): 2252-2257, 2014
Fig. 10: Rtl Simulation Of Pll
We proposed a Novel Low Power Phase Locked
Loop, the proposed new PLL has simpler structure and
lower power dissipation. The dead zone of PLL is less
than 0.01ns and error detection range is not limited.
With no DC leakage current the power consumption is
extenuated and area is drastically reduced. With MOS
transistor count reduced are exponentially reduced.
The Proposed PLL reduces the delay, which improves the
performance of PLL. The designed circuit shows that it is
possible to overcome the issue of PLL short settling time
by using a very low power PFD operating even in idle
mode. So, the recovery time from idle mode to normal
mode is virtually zero. The PFD is designed using 0.8 µm
CMOS technology.
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