FDP on "Analog VLSI design with Cadence Tool"

About the Institute & Department
College of Engineering, Pune (COEP) is one
of the prestigious engineering colleges in
India. Established in 1854, it is the third oldest
engineering college in Asia. It is located in
Pune, Maharashtra. In 2004, the Institute was
granted complete autonomy by the State
Government & declared as Center for
Excellence in Technical Education. The
Institute now is an autonomous engineering
school with permanent affiliation to the
University of Pune.
The Department of Electronics and
Telecommunication Engineering (E&TC) has
been playing a vital role in producing
engineers & technologists of highest caliber
ever since it was established in the year 1948.
The department offers UG programme with 60
intake and two PG programmes with four
specializations (Digital Systems, VLSI &
Embedded Systems, Wired & Wireless
Communication, and Signal Processing) and
Research programmes.
About Entuple Technologies Pvt Ltd
Head Quartered at Bangalore, India, Entuple
Technologies Founded by professionals with a
combined experience of over 80 years in the
Electronics Industry. Combined from the
words "Enable" and "n-tuple", Entuple is
suggestive of enabling multi-dimensional
possibilities & growth for users & all
The management team with its experience in
different sectors such as Telecommunication,
Defense & Aerospace, Power & Utility
OEMS, Research & Academia has joined
together to build a world class team of Next
Generation Solution Enablers in system
technology leaders in such areas also bring
together a dynamic eco-system for users.
India being one of the emerging markets has
been identified as the breeding ground of
leading R&D initiatives in multiple domains.
Entuple is committed to bridge the ever
growing gap in the industry by bringing in
expertise to meet technological challenges by
introducing cutting edge platforms, tools and
About FDP
This FDP focuses on CMOS Analog ICs.
CMOS is the dominant technology for mixed
signal IC design as it provides density &
power savings on the digital side & a good
mix of components for the analog design. This
FDP is designed with a synthesis approach &
it aims at progressive build-up of the
background and makes the learner walk
characterization set of learning activities of
basic analog functional blocks such as current
mirrors, repeaters and finally, a seven-pack
CMOS operational amplifier. The program
also caters to the needs of teachers,
researchers and industry personnel pursuing
their higher studies/research in custom analog
and mixed signal domain.
One of the major challenges faced by the
teachers is in bridging the concepts to the
application and to bring out the practical
perspective for an effective teaching –
learning interaction. This FDP is designed
1. To enable teachers to bridge this gap
through a series of hands–on illustrative
that will help connecting the theoretical
concepts to the industry relevant application
perspective as well as practices.
2. To provide an overview of the topics with
emphasis on opportunities for research,
development and advancement.
3. To provide Hands-on experience on almost
all the tools in Cadence Custom Design flow.
Broad Topics to be covered
 Fundamentals
Processing – CMOS Amplifier Topologies
and Performance
 Small Signal DC Design & Simulation of
the Basic Differential Pair/ Analog Layout
Design Concepts
 Frequency Response & Compensation of
Amplifiers – Performance Analysis
 Mixed Signal Physical Design
 Design & Performance Characterization
of a 7-Pack OPAMP
Resource persons
1. Mr. VD Kulkarni,
Consultant – AMS circuit & System
Design / Training, Entuple Technologies,
2. Mr. Srikar Talla
Senior AE, Entuple Technologies
3. Mr. Binu Allias
FAE, Entuple Technologies
4. Mr. Pramod Sabnis
Director, SoC Implementation, Graphene
Semiconductor Services Pvt.Ltd,
5. Prof. Mukul S. Sutaone
Dean, Alumni, COEP, Pune
6. Prof. Ashok M. Sapkal
Head, Department of E & TC
Engineering, COEP, Pune
Registration form
1. Name: ____________________________
2. Name of College / Industry:
Details of Registration
Faculty – Rs 35,000/Industry personnel - Rs 40,000/The registration fee includes cost towards
course material, lunch, and refreshment.
3. Address__________________________
4. Professional Experience
5. Research interest
5. Email Id: _______________________
6. Mobile Number: __________________
7. DD No. & Bank: __________________
(DD should be drawn in favor of ‘DIRECTOR,
COEP’, payable at Pune)
Declaration by the candidate
The given information is true to the best of my
I agree to abide by the rules and regulations
governing the programme. If selected, I shall
attend the course for the entire duration.
Important Dates to Remember:
Last date for registration: 24/11/2014
Intimation date:
The brochure, application form & technical
details can also be downloaded from college
website: www.coep.org.in
Registration for the FDP can be made by
sending the duly filled application form along
with Demand Draft payable at Pune.
1. Faculty working in Engineering Colleges/
Polytechnic colleges
2. Engineers from R&D Organizations
3. Research Scholars
1. Only 24 participants will be selected on first
come first served basis.
2. Intimation of selection /confirmation will be
only through Email till 28 Nov 2014.
3. If you are selected, the fee paid will not be
refunded under any circumstances.
4. If required, ACCOMMODATION for the
participants will be suggested.
5. No TA/DA will be provided to any participant
The duly filled application form along with
DD is to be sent to:
Ms. Vanita Agarwal
Department of E&TC Engineering
College of Engineering, Pune (COEP)
Wellesley Road, Shivajinagar, Pune-411005
Phone: 020-2550 7663, 09665366195
Fax: 020-2550 7299
Website: www.coep.org.in
Email: [email protected]
TEQIP –II sponsored
One week
Faculty Development Program
“Analog VLSI Design using
Cadence tool”
(Dec 10-14, 2014)
Organized by
Department of Electronics &
Telecommunication Engineering,
College of Engineering, Pune (COEP)
(An Autonomous Institute of the
Government of Maharashtra)
in collaboration with
Course Coordinators
Mrs Vaishali V Ingale (8149477127)
Assistant Prof., E & TC, COEP
Ms. Vanita Agarwal (9665366195)
Assistant Prof., E & TC, COEP
Mr. Shatrughan Ransubhe (9960663802)
Regional Sales Manager,
Entuple Technologies, Pune