HOMEWORK 6 CMPEN 411 Due: 3/6/2014 11:30pm Learning Objective Use the VLSI CAD tools to design and implement the 8 bit RISC microprocessor datapath consisting of an 8 bit 4-to-1 MUX, a dual port RAM, and an add/sub circuit, and analyze it. Instruction This semester, we are building a simple microprocessor shown below. It is an 8-bit RISC processor, its full description and specification is posted at: http://www.cse.psu.edu/~kyusun/class/cmpen471/11f/hw/pj7/pj7.html Design and implement the 8 bit RISC microprocessor datapath shown below consisting of the 8 bit 4-to-1 MUX, the dual port RAM (Homework 5), and the add/sub circuit. Read all of the following instructions before starting the design. An 8 bit RISC Microprocessor Data Path 1. Dual port RAM with 8 words from the Homework 5 should be reused. Given an address, the address decoder generates the selection signal, only one word is selected in each port. 2. Design the datapath by integrating the three components: the 8 bit 4-to-1 MUX, the dual port RAM (Homework 5), and the add/sub circuit. The details of the add/sub circuit is shown below. The 8-bit Add/Sub Circuit 3. Using the Cadence tool Virtuoso, design the 8-bit dathpath circuit schematic and layout. The design must be free from the DRC errors and pass the LVS checking. 4. To verify the functioning, design the Hspice simulation files: .hsp, .s, and .sp files. Your simulation output must show idat1, idat2, sdat, ddat, adat, mux output, dx1, dx0, mdw, sub, and c. Design your .hsp file to show that MV, ADD, and SUB instructions are working correctly. Explain your instruction sequence with the control signals dx0, dx1, mdw, and sub. (A sample Hspice test file is posted here: sample .hsp file.) 5. What is the instruction execution time? What is the clock cycle time? What is the worst case cycle time? Which component is the slowest? Why does it take so long? How can we make it faster? Design the .hsp file to demonstrate the fastest clock times of the datapath while maintaining the correct output result. What limits the maximum speed of operation? Show the simulation plot to substantiate your answer. 6. How many transistors are used in your datapath design? 7. Did you use static, dynamic, or pass transistor logic? 8. Are there any errors in schematic? 9. Is there an error in layout? Does your layout pass the DRC checking without errors? 10. Is there a miss match on the schematic versus layout? Does your design pass the LVS checking without errors? 11. Extract the circuit from the layout including the parasitic capacitances. Then hspice simulate the extracted circuit netlist. What is the worst case output signal rise time, fall time, and delay time? The worst case delay time is from which input to which output? Explain the signal path for the worst case delay time (this is called critical signal path)? Worst case delay time: T = ______ nSec. 12. Use hierarchical design method to manage design complexity. That is, design simple cells and design top cell which combines simple cells. The Cadence tool Virtuoso assumes all design is done this way, uses cellview to manage cells. Use meaningful names for the cells; for example, use ‘dpram8x8’ rather than ‘hw5’ for the dual port RAM register. 13. Homework 6 preparation: Create a directory hw6yourlastname under c411 directory (assuming you have c411 directory in your home for this class). Change the current directory to hw6yourlastname. Set up the directory for a new Cadence Virtuoso library. Then start the hw6 design project. For example, my hw6 directory will be hw6choi and I will be running the following unix commands right after I login to my account: % % % % % cd c411 mkdir hw6choi cd hw6choi runcds virtuoso & You can follow the same except that you need to use your last name after 'hw6'. Collect all the components in this directory, it will be 'tar' and zipped, turn-in to the instructor for grading. This way, you can collect all the files within the hw6yourlastname directory and it will allow the grading. Otherwise, any missing files may cause your design verification for grade to fail. You may lose points if your turned-in hw6 design files cannot be verified by grader. 14. Create a hw6 report file hw6yourlastname.doc and include captured image of layout and the simulation results. Add your explanations and comments. On the Linux machines in room 218 IST, one can use 'openoffice.org' program for the document creating and editing, and use 'gimp' program for the image capture and processing from the screen. 15. The hw6 report file must also include the answers to the questions. 16. The hw6 report file can be in .doc or .pdf, must include a cover page for student information such as 'CMPEN 411’, ‘Homework 6’, your name, etc. Please use the sample Homework 6 report format, the sample hw6 report file is posted: Sample hw6 Report 17. Create a tarred zip file of your hw6yourlastname directory in c411 directory. It will contain the schematics, symbols, layouts, .hsp, .sp files, and .doc report file. In your c411 directory, use the following unix commands % tar -czvf hw6yourlastname.tgz hw6yourlatname to create a tarred zip file of hw6yourlastname library. For example, % tar -czvf hw6choi.tgz hw6choi will archive the directory hw6choi and create a zipped file hw6choi.tgz in my c411 project directory. For the grading, the command ‘tar –xzvf hw6choi.tgz’ will be used to restore project. You must delete .tr0 files before zipping, for their sizes are usually large. 18. Turn-in your project zip file through Penn State ANGEL. Deposit your zip file into the Homework 6 DropBox under CLASS tab in CMPEN 411 Course. 19. Make sure that you include all the files necessary into your project folder, in order to verify for grading. Turn-in your project before 11:30pm on the due date.
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