### QB_VLSI - WordPress.com

```EC Dept.
Hasmukh Goswami College of Engineering
Subject: VLSI Technology & Design
Questions from Previous Exam Papers
Unit 2: Fabrication of MOSFET
1. Explain fabrication process of nMOS with diagrams.
2. Draw the flow chart for the fabrication of n-well CMOS integrated circuit
which includes the each and every step.
3. Discuss basic steps of LOCOS process.
4. Draw the layout of CMOS inverter and calculate the minimum silicon area
required by this circuit as per the Lambda Design Rules.
5. Discuss the basic steps of fabrication.
Unit 4: MOS Inverters: Static Characteristics
1. Explain the functioning of depletion type NMOS inverter and derive critical
voltage points VOH, VOL, VIL and VIH for the same.
2. Design a CMOS inverter to operate at supply voltage of 10V, with KR=1/4,
VTP=-1V, VTN=0.8V
3. Determine the logic levels and critical voltages for DN MOSFET load
inverter with VDD=5V. Use the following parameters: Kd=75µA/V2,
VTD=1V, KL=25µA/V2, VTL =-2V
4. Design a resistive load inverter with R=1KΩ, such that VOL=0.6V. The
enhancement type NMOS driver transistor has the following parameters:
VDD=5.0V, VTO=1.0V, γ=0.2V1/2, λ=0, µ nCox=22µA/V2. Find the required
aspect ratio, W/L, VIL, VIH and noise margins NML and NMH.
5. Draw two types of Enhancement Load inverter circuits and compare both.
Why enhancement Load inverter nMOS inverters are not used in large scale
digital application?
6. Draw the CMOS inverter circuit and Voltage Transfer Characteristic (VTC)
for different operating regions of the nMOS and pMOS transistors. Derive
critical voltage points VOH, VOL, VIL and VIH.
H.G.C.E
1
Prepared By: Dharmendra Patel
EC Dept.
7. Consider a CMOS inverter circuit with the following parameters: VDD=3.3V,
VTO,n=0.6V,VTO,p=-0.7V, µ nCox=60 µA/V2, µ pCox=25 µA/V2, (W/L)n=8 and
(W/L)p=12. Calculate the noise margin and the switching threshold (VTH) of
the circuit.
8. Determine the minimum supply voltage (VDD) up to which CMOS inverter
will continue to operate correctly and its voltage transfer characteristic will
not show any hysteresis.
9. Consider a CMOS inverter circuit with the following parameters: VDD=3.3V,
VTO,n=0.6V,VTO,p=-0.7V, kn=200 µA/V2, kp=80 µA/V2. Calculate the noise
margin of the circuit.
10. Explain the design of symmetric CMOS and show that (W/L)p = 2.5 (W/L)n
for unity KR value. Also show the relationship between NML, NMH and VIL
for such case.
11. Discuss and compare inverter designs with different types of loads.
Unit 5: MOS Inverters Switching characteristics and Interconnect Effects
1. For a CMOS inverter, define propagation delay times with appropriate
figures and waveforms and show its calculations using average capacitance
current charge down and charge up equations.
2. Derive the expression for delay times tPHL and tPLH for CMOS inverter
assuming step input with zero rise and fall time.
3. Explain Switching Power Dissipation of CMOS Inverters with circuit
diagram and typical input and output waveforms and also explain power
delay product.
4. Discuss CMOS Ring Oscillator with necessary waveforms.
5. What is the simple thumb rule to determine the model for interconnection
lines to estimate interconnect delay and describe in brief.
6. Write down and explain Elmore delay formula. Calculate the Elmore delay
from input to output node for simple RC ladder network consisting N
identical stages, where each stage consists of resistance with a value R/N
and capacitance to C/N.
7. Explain estimation of interconnection parasitic in brief.
H.G.C.E
2
Prepared By: Dharmendra Patel
EC Dept.
Unit 9: Chip I/P and O/P Circuits
1. Discuss the various techniques available for on chip clock generation and
distribution for successful high-speed VLSI design.
2. List at least five considerations for digital system design, which should be
taken into account in order to achieve high speed VLSI design.
3. Explain the latch-up problem in CMOS inverters. Also mention the causes
for latch-up and guidelines to avoid it.
Unit 10: Design for testability
1.
2.
3.
4.
5.
Discuss controllability and observability.
Explain fault types and models.
Explain Ad HOC testable design techniques.
Explain Built In Self Test (BIST) Techniques.
Discuss Scan techniques for testing.
Unit 11: Introduction to Programmable Logic Devices
1. Define the terms: FPGA, CPLD, PLA and PAL.
2. Draw and explain the basic structure of FPGA. Explain the functioning of
Logic Cell using lookup table approach. Comment on signal delays in
FPGA.
3. Draw and explain the basic structure of CPLD. Also explain PAL-like block
in brief.
H.G.C.E
3
Prepared By: Dharmendra Patel
```