ISSN (Online) : 2278-1021 ISSN (Print) : 2319-5940 International Journal of Advanced Research in Computer and Communication Engineering Vol. 3, Issue 2, February 2014 Multicarrier Sinusoidal PWM Technique Based Analysis of Asymmetrical and Symmetrical 3Ф Cascaded MLI 5 V.Bhuvaneswari1,M.E.HariKumar2, A.ShakilAhmed3, R.Vinoth4, Ajith.B.Singh Assistant professor, EEE, Sree Sowdambika College of Engineering, Chettikurichi, Tamilnadu, India1 Assistant professor, E&I, Sethu Institute of Technology, Kariapatti, Tamilnadu, India 2,3,4,5 Abstract: This work proposes a comparison study of cascaded H-bridge multilevel inverter (CHBMLI) in which symmetrical and asymmetrical arrangement of five level and seven level H-bridge inverters are compared in order to find an optimized output voltage quality with lower harmonic distortion. Several studies have been conducted on the three phase cascaded symmetrical multileve l inverter (MLI).However, there are few studies that actually discuss or evaluate the performance of three phase H-bridge asymmetrical MLI. Here, three multicarrier pulse width modulation (PWM) techniques such as constant switching frequency, variable switching frequency and phase shifted PWM are proposed. MATLAB/SIMULINK software is used for simulation. The carried out simulation studies shows that an asymmetrical configuration provides high output voltage with very low total harmonic distortion (THD) using less switching devices. Keywords: MLI, PWM, Multi Carrier, MATLAB, THD I. INTRODUCTION Multilevel inverter is a power electronic converter built to synthesize a desired AC voltage waveform from several levels of DC voltages. Here, the DC levels were considered to be identical in that all of them were batteries, solar cells, capacitors etc [1] [2]. Some medium voltage motor drives and utility applications require medium voltage and megawatt power level. For a medium voltage grid, it is troublesome to connect only one power semiconductor switch directly. As a result, a multilevel power converter structure has been introduced as an alternative in high power and medium voltage situations. Multilevel inverter not only achieves high power ratings, but also enables the use of renewable energy sources. Renewable energy sources such as photovoltaic, wind, fuel cells can be easily interfaced to a multilevel inverter system for a high power application [1][3]. The output voltage quality of the MLI is improved as the number of voltage level increases, so the quantity of output filters can be decreased. On the other hand, solutions with a low number of levels need a large and expensive LC output filter [4].A multilevel inverter has several advantages over a conventional two level inverter that uses a high switching frequency PWM. Multilevel inverter not only generates the output voltage with very low distortion, but also can reduce the dv/dt stresses; therefore electromagnetic compatibility (EMC) problems can be reduced. It can operate at both fundamental frequency and high switching frequency PWM. One particular disadvantage is that it requires more number of power semiconductor switches. The most common topologies of MLI are Diode-Clamped or Neutral Point Clamped MLI, Flying capacitor MLI and Cascaded H-bridge MLI [5]. The cascaded inverter has drawn great interest due to the great demand of medium-voltage high-power inverters. With an aim to reduce the number of dc sources required for the cascaded MLI, this paper focuses mainly on Copyright to IJARCCE asymmetric MLI that uses unequal dc sources in each phase to generate a seven level equal step multilevel output[11]. In symmetrical MLI, all H-bridge cells are fed by equal voltages and hence all arm cells produce similar output voltage steps[9]. In asymmetrical MLI, all arm cells are not fed by equal voltages. In this inverter, the arm cells have different effect on the output voltage. To provide a large number of output levels without increasing the number of inverters, asymmetric multilevel inverters can be used. It is proposed to choose the dc-voltages sources according to a geometric progression with a factor of 2 or 3[4][12]. I. THREE PHASE CASCADED MULTILEVEL INVERTER A basic structure of a cascaded MLI is shown in Fig.1. Fig. 1 Three phase cascaded multilevel inverter It synthesizes a medium voltage output based on a series connection of power cells which use standard low voltage component configurations. Each SDC (separate DC source) is associated with a single-phase full-bridge inverter. The ac terminal voltages of different level inverters are connected in series. Through different combinations of the four switches, S1www.ijarcce.com 5755 ISSN (Online) : 2278-1021 ISSN (Print) : 2319-5940 International Journal of Advanced Research in Computer and Communication Engineering Vol. 3, Issue 2, February 2014 S4, each converter level can generate three different voltage outputs, +Vdc, -Vdc and zero. The AC outputs of different full-bridge converters in the same phase are connected in series such that the synthesized voltage waveform is the sum of the individual converter outputs. V0 (t) =V0, 1(t) + V0, 2(t) +………. +V0, N (t) the carrier signals. If the reference wave is greater than a carrier signal, then the active device corresponding to the carrier are switched on. Otherwise the devices switch off. The frequency ratio mf is defined as mf=fc/fm. The amplitude modulation index ma is defined as ma=2Am/ (m(1) 1) Ac. IV. CONTROL TECHNIQUES FOR ASYMMETRICAL MLI If the voltage sources in Fig.1 are Vdc and 2Vdc, then it If all the voltage sources in Fig.1 are equal to Vdc then the is asymmetrical MLI and it produces seven levels of inverter becomes symmetrical MLI. The effective number output voltage such as +3Vdc, +2Vdc, +Vdc, 0,-Vdc, -2Vdc,of output voltage levels m in symmetric multilevel inverter 3Vdc. The control techniques for asymmetrical MLI are as is given by follows. m=2N+1 (2) A. Constant Switching Frequency PWM (CSFPWM) The maximum output voltage is then, The constant switching frequency pulse width modulation technique is most popular and very simple V0max=N Vdc (3) switching scheme. For m level inverter, all (m-1) carriers If the voltage sources V1, V3, V5 is equal to Vdc and V2, V4 use same frequency fc and the same amplitude Ac and they and V6 is equal to 2Vdc the inverter becomes are disposed such that the bands they occupy are asymmetrical. The number of output voltage levels m in contiguous. It is further subdivided into asymmetric multilevel inverter is given by Phase Disposition PWM (PDPWM) m= -1, if Vdc, j= Vdc (4) Phase Opposition Disposition PWM(PODPWM) Alternate Phase Opposition Disposition The maximum output voltage of this N cascaded PWM(APODPWM) multilevel inverter is given by 1) PDPWM: In PDPWM technique, all triangular V0max = (5) dc, j carriers are arranged in phase. 2) PODPWM: In PODPWM technique, the carriers above the zero reference are in phase, but shifted III. MULTICARRIER MODULATION STRATEGIES by 180 below the zero reference. The proposed asymmetric MLI is performed using 3) APODPWM: In APODPWM technique, each multicarrier modulation techniques [6]. Three techniques triangular carrier is shifted by 180 from its such as constant switching frequency, variable switching frequency and phase shifted PWM [7] are implemented. adjacent carrier. Carriers used in MLI may be vertically shifted or horizontally shifted. In this paper, both vertical shifted and horizontal shifted carriers are taken for the analysis. The general principle of a carrier based PWM is the comparison of a reference waveform with a carrier waveform, this typically being a triangular waveform [8]. The carrier frequency defines the switching frequency of the converter and the high order harmonic component of the output voltage. Time(s) Fig.2 CSF PDPWM Subharmonic PWM is otherwise known as sinusoidal PWM (SPWM). Sinusoidal PWM for MLI is based on classic two level SPWM. But, the difference between two level SPWM and multilevel SPWM is the number of carriers used in multilevel SPWM. For an m-level inverter using bipolar multicarrier technique, (m-1) carriers with the same frequency fc and same peak to peak amplitude Ac are used. The reference waveform has the amplitude Am and frequency fm and it is centred above the zero level. Time(s) Fig.3 CSF PODPWM The reference wave is continuously compared with each of ))) Amplitude Amplitude where N is the number of cascaded bridges. Copyright to IJARCCE www.ijarcce.com 5756 ISSN (Online) : 2278-1021 ISSN (Print) : 2319-5940 International Journal of Advanced Research in Computer and Communication Engineering Vol. 3, Issue 2, February 2014 Amplitude V. SIMULATION In order to analyse and to test the proposed topology, simulations are conducted by MATLAB/SIMULINK software. The above mentioned PWM techniques have been implemented for both three phase five level symmetrical and seven level asymmetrical multilevel inverter. Fig.4 CSF APODPWM Time(s) A.Design Parameters Amplitude The simulation parameters for three phase symmetrical Fig.2 to Fig.4 shows the multicarrier signal for constant multilevel inverter with RL load are as follows switching frequency PWM techniques. Input DC voltage, Vdc =100V Reference switching frequency, fm =50Hz B. Variable Switching Frequency PWM (VSFPWM) Carrier switching frequency, fc =2 kHz The number of switching for upper and lower devices is Three Phase Load, R =15 Ώ, L=25mH much more than that of intermediate switches in constant switching frequency carriers. In order to equalize the The simulation parameters for three phase asymmetrical number of switching for all switches, variable frequency multilevel inverter with RL load are as follows PWM is used. Here the carrier sets C1 and C6 will have the same frequencies, C2 and C5 will have the same Input dc voltage, Vdc1=100V & frequencies and C3 and C4 will have the same Vdc2=200V frequencies.Fig.5 shows the multicarrier signal for Reference switching frequency, fm =50Hz variable switching frequency PWM. Carrier switching frequency, fc =2 kHz Three Phase Load, R =15 Ώ, L=25mH B.Symmetrical MLI To verify the results of symmetrical MLI, simulations have been conducted for several multicarrier PWM techniques as mentioned above. The five level output voltage waveforms of the symmetrical MLI are shown in Fig.7. C.Phase Shifted PWM (PSPWM) Amplitude Each cell is modulated independently using unipolar and bipolar pulse width modulation respectively, which provides the even power distribution among the cells. A carrier phase shift of 180 /m is introduced across the cells to generate stepped multilevel output with lower distortion[10].Fig.6 shows the multicarrier signal for phase shifted PWM. It uses m-1 carriers with same amplitude and frequency which are shifted by 90 to one another to generate the output voltage. Voltage(v) Time(s) (a) (b) Fig.6 PS PWM Copyright to IJARCCE Time(s) Voltage (v) Fig.5 VSF PWM Time(s) Time(s) www.ijarcce.com 5757 ISSN (Online) : 2278-1021 ISSN (Print) : 2319-5940 Voltage (v) International Journal of Advanced Research in Computer and Communication Engineering Vol. 3, Issue 2, February 2014 (e) (c) Time(s) Fig.7. Output phase voltage waveform for symmetric MLI (5 level) using (a) Constant switching frequency (b)Variable switching frequency (c)Phase shifted PWM The total harmonic distortion of the above techniques are observed using FFT analysis. The voltage and current harmonic spectrums are shown in Fig.8. (f) Fig.8. Voltage and current harmonic spectrum for (a) & (b) Constant switching frequency (c) & (d) Variable switching frequency (e) & (f) Phase shifted PWM (a) (b) MLI To verify the proposed asymmetrical MLI, simulations have been conducted for several multicarrier PWM techniques and the obtained results are compared with symmetrical MLI. Fig.9 shows the output phase voltage waveform for constant switching frequency PWM technique. Voltage(v) C.Asymmetrical (c) Time(s) Voltage(v) (a) (b) Time(s) (d) Copyright to IJARCCE www.ijarcce.com 5758 ISSN (Online) : 2278-1021 ISSN (Print) : 2319-5940 Voltage(v) International Journal of Advanced Research in Computer and Communication Engineering Vol. 3, Issue 2, February 2014 Time(s) (c) (e) Fig.9. Output phase voltage waveform for constant switching frequency asymmetric MLI (7 level) using (a) PDPWM (b)PODPWM (c)APODPWM The voltage and current harmonic spectrums for various constant switching frequency PWM techniques is shown in Fig.10. (f) Fig.10. Voltage and current harmonic spectrum for constant switching frequency (a) & (b) PDPWM (e) & (d) PODPWM (e) & (f) APODPWM Voltage(v ) (a) Figure.11 shows the seven level output voltage waveform for variable switching frequency PWM and phase shifted PWM. (b) Time(s) (b) Time(s) Voltage(v ) (a) (c) Fig.11. Output phase voltage waveform for asymmetric MLI (7level) using (a) Variable switching frequency (b) Phase shifted PWM (d) Copyright to IJARCCE The voltage and current harmonic spectrums for variable switching frequency and phase shifted PWM is shown in Fig.12. www.ijarcce.com 5759 ISSN (Online) : 2278-1021 ISSN (Print) : 2319-5940 International Journal of Advanced Research in Computer and Communication Engineering Vol. 3, Issue 2, February 2014 TABLE I PERFORMANCE COMPARISON OF SYMMETRICAL AND ASYMMETRICAL MLI (a) VI. CONCLUSION In this paper, three different schemes the constant switching frequency, variable switching frequency and phase shifted pulse width modulation are incorporated. Indeed, symmetrical and asymmetrical arrangements of five and seven level H-bridge inverters have been Symmetrical (b) (c) (d) Fig.12. Voltage and current harmonic spectrum for (a) & (b)Variable switching frequency (c) & (d) Phase shifted PWM The root mean square (RMS) value of the output voltage and total harmonic distortion of voltage and current were compared for both symmetrical MLI and asymmetrical MLI. Table I shows the performance comparison of symmetrical and asymmetrical multilevel inverter. The readings were taken for various values of R and RL loads. The maximum output voltage for the symmetrical multilevel inverter is 150.3V and for asymmetrical multilevel inverter it is 218.2V.The minimum voltage and current harmonic for symmetrical MLI is 25.76% and 8.35% respectively. The minimum voltage and current harmonic for asymmetrical MLI is 15.28% and 1.59% respectively. From the Table I it is clear that, by using same circuit configuration the magnitude of the output voltage is greater in asymmetrical MLI than symmetrical MLI and it also shows that the total harmonic distortion is lesser in asymmetrical MLI. Copyright to IJARCCE Asymmetrical THDV (%) THDI (%) V0 THDV (%) THDI (%) V0 CSFPD 26.91 8.67 146.8 16.37 2.15 215.6 CSFPOD 26.26 8.67 146.2 15.28 1.97 215.2 CSFAPOD 26.11 8.35 146.5 16.17 1.86 216.0 VSFPWM 27.18 8.44 146.6 16.03 2.88 216.4 PSPWM 25.76 18.45 150.3 24.51 1.59 218.2 compared in order to find an optimum arrangement with lower harmonic distortion and optimized voltage quality. It is clear from the simulation results that the asymmetrical configuration provides nearly sinusoidal voltages with very low voltage and current harmonics when compared to symmetrical MLI. Also, it is confirmed that the number of switches for symmetrical and asymmetrical multilevel inverter is same. For same circuit configuration, the magnitude and number of levels of the output voltage of asymmetrical MLI is higher than that of the symmetrical MLI. [1] [2] [3] [4] [5] [6] [7] REFERENCES J. S. Lai and F. Z. Peng, “Multilevel Converters-A new Breed of Power Converters,” IEEE Trans. Ind. Applications., vol.32,pp. 509- 517, May/June 1996. P.Thongprasri,” A 5-Level Three-Phase Cascaded Hybrid Multilevel Inverter,” International Journal of Computer and Electrical Engineering, Vol. 3, No. 6, December 2011. J. Rodriguez, J. S. Lai and F. Z. Peng, “Multilevel Inverters: Survey of Topologies, Controls, and Applications,” IEEE Transactions on Industry Applications, vol. 49, no. 4, Aug. 2002, pp. 724-738. Farid khoucha, Mouna soumia lagoun, Abdelaziz kheloui, ”A comparison of Symmetrical and Asymmetrical three phase HBridge Multilevel Inverter for DTC Induction Motor Drives,” IEEE Trans. Energy conv.,vol.26,no.1,March 2011. Mariusz Malinowski, Senior Member, IEEE, K.Gopakumar, Senior Member, IEEE, Jose Rodriguez, Senior Member, IEEE, and Marcelo A. Pérez, Member, IEEE,” A Survey on Cascaded Multilevel Inverters”, IEEE Trans on Industrial Electronics, vol. 57, no. 7, July 2010. Brendan Peter McGrath, Student Member, IEEE, and Donald Grahame Holmes, Member, IEEE,” Multicarrier PWM Strategies for Multilevel Inverters”, IEEE Trans on Industrial Electronics, vol. 49, no. 4, August 2002. Roozbeh Naderi and Abdolreza Rahmati,” Phase-Shifted Carrier PWM Technique for General Cascaded Inverters,” IEEE Trans on power Electronics, vol. 23, no. 3, May2008 www.ijarcce.com 5760 ISSN (Online) : 2278-1021 ISSN (Print) : 2319-5940 International Journal of Advanced Research in Computer and Communication Engineering Vol. 3, Issue 2, February 2014 [8] [9] [10] [11] Giuseppe carrara, Simone Gardella, Mario Marchesoni, Member, IEEE, Raffaele Salutari, and Giuseppe Sciutto,” A New multilevel PWM method: A theoretical analysis”, IEEE Trans on power Electronics, vol. 7, no. 3 July 1992. P. Palanivel, S. S. Dash,” Analysis Of THD and Output voltage performance for cascaded multilevel inverter using carrier pulse width modulation techniques, ”IET power Electron.,vol.4,iss.8,pp.951-958,March 2011. Roozbeh Naderi and Abdolreza Rahmati,” Phase-Shifted Carrier PWM Technique for General Cascaded Inverters,” IEEE Trans on power Electronics, vol. 23, no. 3, May2008. Rao S.N, Kumar D.V.A, Babu C.S,“ New Multilevel inverter topology with reduced number of switches using advanced modulation strategies ,” ICPEC, no.693-699,Feb 2013. Belkamel.H, Mekhilef.S, Masaoud.A, Naeim.M.A, “Novel three phase asymmetrical cascaded multilevel voltage source inverter,” IET power Electron, vol.6, iss.8, pp.1696-1706, Sep 2013. R.Vinoth is an assistant professor at Sethu Institute of Technology. He received his B.E degree in Instrumentation and Control Engineering from Arulmigu Kalasalingam College of Engineering and M.E degree in Industrial Engineering from Thiagarajar College of Engineering. He has attended various national conferences and International Conferences. He has published one international journal. Ajith.B.Singh is an assistant professor at Sethu Institute of Technology. He received his B.E degree in Electronics and Instrumentation Engineering from Kamaraj College of Engineering and BIOGRAPHIES Technology and M.E degree in Control and Instrumentation from Kalasalingam University. He V.Bhuvaneswari is an assistant has presented papers in numerous national and professor at Sree Sowdambika College international conferences, and also published a book and of Engineering. She received her B.E various international journals. degree in Electrical and Electronics Engineering from Kamaraj College of Engineering and Technology and M.E. degree in Power Electronics and Drives from Mepco Schlenk Engineering College in 2010 and 2013 respectively. She holds university rank in masters degree. She attended various national conferences and presented one paper in National Conference. [12] M.E.HariKumar is an assistant professor at Sethu Institute of Technology. He received his B.E degree in Electronics and Instrumentation Engineering from Kamaraj College of Engineering and Technology and M.E. degree in Computer and Communication in 2006 and 2008 respectively. He is a Student Chapter Incharge in ISOI. He has been awarded the Best IEEE Student member while doing masters degree. He attended various national conferences and presented one paper in International Conference. He has published one international journal and two international conferences. A.Shakil Ahmed is an assistant professor at Sethu Institute of Technology. He received his B.E degree in Electronics and Communication Engineering from K.L.N College of Information Technology and M.E degree in Communication Systems from Coimbatore Institute of Technology. He has been awarded the best student award while doing his master degree. He has attended various national conferences and presented two papers in International Conference and also published one paper in IEEE and one international journal. Copyright to IJARCCE www.ijarcce.com 5761

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