here - CSH Consulting LLC

CSH Consulting, LLC
Signal Integrity Consulting
January 2015
www.cshconsulting.net
[email protected]
603-494-9277
Overview
•
High Speed Serial Channel Modeling
– Ethernet, PCIe GenX, Fibre Channel, SAS, USB
– Anything over 2Gb/s requiring frequency domain simulation and
modeling.
•
High Speed Memory Simulation
– DDR2, DDR3, DDR4
– Clock, Address, Data, Data Strobe
– Buffer Strengths, On Die Termination, Topology, Waveform Integrity,
Setup and Hold Mask Evaluations for DQ and
Command/Control/Address.
– Intelligent EBD file translation and debugging.
•
Power Integrity Simulation
– DC Analysis and Frequency Response Analysis of Power Planes
•
CAD Guidelines
– Concise recommendations for PCB Layout based on Pre-Layout
Simulations.
Simulation Capability
• Software Resources
–Agilent ADS
• Statistical Eye simulation using IBIS-AMI Models
–Ansys HFSS
•3D Modeling of structures (vias, AC Caps, BGAs, Connectors)
•3D Modeling of pcb etch.
•In-house automation ensures faster response and consistency
–Ansys SIwave
•Power Plane Voltage Drop simulation
•Power Plane Frequency analysis and decoupling capacitor optimization
–Apsim RLGC
•2D Modeling of PCB Transmission Lines
•Frequency-dependent W-elements
–HSpice
•Time Domain Simulation using IBIS and AMI.
•Frequency Domain Simulation
– Concatenation of S-Parameters
Channel Modeling - Process and Tools
BGA
Package
BGA Via
Transition
Via
PCB
Etch
Connector
Footprint
Connector
Connector
Footprint
Backplane
Etch
BGA
Package
PCB
Etch
AC Cap
PCB
Etch
Connector
Footprint
Connector
• Link Models created in HSpice
–Cascaded S-parameters of connector, footprint, etch
• Connector Models
–Provided by Connector Vendor in Touchstone format.
• PCB Footprints
–Simulated in Ansoft HFSS
• Each one is different!
• PCB Etch Models
–Tabular W-element RLGC Models generated in Apsim
RLGC.
–De-Embedded S-parameter Model generated in HFSS
Connector
Footprint
Passive Channel Design Drivers
•
Insertion Loss
– Driven by PCB material property and via stubs.
•
Return Loss
– Driven by Impedance mismatches mainly arising in component footprints.
•
Crosstalk
– Unwanted electromagnetic coupling between traces, vias and connector
contacts.
•
Skew
– Driven by routing, connector, and PCB laminate material.
•
Common Mode Conversion and EMI
– Driven by unbalanced differential pairs in routing and connectors.
PCB Material Property Extraction From Measurements
Insertion Loss vs PCB and Cable Material
Loss Characteristic of 1m of Copper Medium
0
-5
-10
-15
High Confidence Region
(< 30dB)
-20
-25
Magnitude (dB)
-30
Near Limit ( 30-40dB)
-35
-40
No Operation
-45
-50
-55
-60
-65
26AWG EXD
Megtron-7NE RA
Megtron-7NE
Megtron-6 FlatBond
-70
-75
-80
0
2.5
5
7.5
Length: 1m
Line Width: 6.5mil
Line Space: 8.5mil
Copper Weight: ½ oz
10
12.5
15
Frequency (GHz)
17.5
20
22.5
25
Insertion Loss vs. Line Width
Magnitude (dB)
Megtron 6 Insertion Loss: 40 inches
0
-2
-4
-6
-8
-10
-12
-14
-16
-18
-20
-22
-24
-26
-28
-30
-32
-34
-36
-38
-40
sdd12-5p5
sdd12-6p5
0
1
2
3
4
5
6
7
8 9 10 11 12 13 14 15 16 17 18 19 20
Frequency (GHz)
Crosstalk Sources
3h-5h
h
1. Between Differential Pair Traces
– Crosstalk Target < = -50dB
2. Between Vias in Footprint
– Simulate and Tune
• Antipad shapes
• Drill size
• Pad Size
• Backdrill Depth
3. Within Connectors
– Simulate and tune conductor geometry,
plastic materials and return paths.
FEXT Contributors (GH2 Driven)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
2
4
6
Frequency (Hz)
8
10
9
x 10
DC Blocking Capacitor Example
Cap
Clearance
Finished Dia
6.0mil
Diff Port Zo
100
Material
Drill Dia
9.8mil
Layer Escape
10
Dk
3.85
0.009
Pad Dia
20.0mil
Line Width
9.00mil
Df
Antipad Dia
45.0mil
EtchBack
0.1mil
Layers
Oval Dogbone
45.0mil
Line Space
10.0mil
Thickness
Megtron-4
14
64.4 mil
0402
Layer 2
DC Blocking Capacitor Example Results
Insertion Loss, Return Loss and TDR
Differential Insertion and Return Loss: RX Cap L1 / L10 Escape
0
Time Domain Waveform: RX Cap L1 / 10
110
-10
105
Goal
100
95
-30
Ohms
Magnitude (dB)
-20
90
93 ohms
-27dB at 6GHz
85
-40
80
-50
75
Simulated Differential TDR
sdd12
70
sdd11
0
-60
0.05
0.1
0.15
Time(nS)
0
5
10
15
20
Frequency (GHz)
25
30
35
40
0.2
0.25
0.3
IEEE 802.3ap KR (10Gbps): Insertion Loss and ILD
Channel Example
Insertion Loss Deviation: Sim0102 R1
5
-5
4
-10
3
-15
2
Magnitude (dB)
Magnitude (dB)
Insertion Loss: Sim0102 R1
0
-20
-25
-30
-35
-40
-45
-50
0
1
0
-1
-2
-3
Simulated Link
Simulated Link LS
IL Mask High
IL Mask Low
2
4
6
Frequency (GHz)
-4
8
10
-5
1
Simulated Link
IL Deviation High
IL Deviation Low
2
3
4
Frequency (GHz)
5
6
IEEE 802.3ap KR (10Gbps): Return Loss and ICR
Channel Example
Return Loss: S im0102 R1
0
80
Simulated Link
Return Loss Mask
70
-10
60
-15
50
Magnitude (dB)
Magnitude (dB)
-5
-20
-25
40
30
-30
20
-35
10
-40
10
-1
0
10
Frequency (GHz)
1
10
0
-1
10
Simulated Link
Simulated Link LS
ICR Mask
0
10
Frequency (GHz)
10
1
0
0
-10
-5
-20
-10
-30
-15
Magnitude (dB)
Magnitude (dB)
IEEE 802.3bj (25Gbps) Insertion and Return Loss
Channel Example
-40
-20
-50
-25
-60
-30
-70
-35
Simulated Link
Simulated Link
IL Mask
RL Mask
-80
-40
0
5
10
15
Frequency (GHz)
sdd12=s16ptest.sdd(:,2,1);
20
25
0
5
10
15
20
Frequency (GHz)
sdd11=s16ptest.sdd(:,2,2);
25
IEEE 802.3bj (25Gbps) Crosstalk and ICR
Channel Example
0
0
Next1= 2,4. Next2= 2,8. Next4= 4,6. Fext3= 2,5.
-5
-10
Next1x2, Next2x2, Next4x2, Fext3x2
-20
-15
-30
-20
Magnitude (dB)
Magnitude (dB)
-10
-40
-50
-60
-70
-25
-30
-35
-40
-45
-50
Next1
-80
-90
-100
30.0dB @ 12.5GHz
0
10
20
Frequency (GHz)
30
-55
Next2
Next4
-60
Fext3
-65
40
-70
Sdd21
TotalXTK:RMS
0 2 4 6 8 1012 141618 20222426 283032 343638 40
Frequency (GHz)
Channel TDR
Channel Example
110
105
100
Ohms
95
90
85
80
Simulated Differential TDR
75
0
1
2
3
4
Time (nS)
5
6
7
SIwave: Power Plane Voltage Drop
SIwave: Power Plane Impedance vs. Frequency
Power Plane Impedance at U2. File: ..\Plane_Only_SYZ.xls
1000
100
Impedance (ohms)
10
1
Goal: 0.080ohm @ 40.0MHz.
0.1
0.01
Plane Only
Plane With Caps
Goal
0.001
0.1
1
10
Frequency (MHz)
100
1000
ADS Schematic:
1 Million Bit-By-Bit Simulation
Statistical Eye: 12.5Gbps
1 Million Bit-By-Bit Simulation
Amplitude: 336mV
Width: 63ps
Width: 0.79UI
Statistical Eye: 6.25Gbps
Measurement vs. Simulation
Measurement
240mV
0.76UI
162mV
0.70UI
Simulation
(from LinkEye)
DDR3 Address Path Topology Example
Micron v68a.ibs
Input Model: INPUT_1333
0.75V
Freescale P1021
U2
U3
N3
L6
0Ω
U1
0.022”
40ohm
12
5.0mil
FreeScale P1021 IBIS Model: P1021 Ibis Model.ibs
Zo
Layer
Width
N3
0.022”
0.540”
Zo
Layer
Width
Model: ddr3_drvr_40
N3
0.022”
1.446”
U4
0.552”
40ohm
3
5.0mil
0.160”
39Ω
Volts
1333 MT/s DDR3 Address/Clk Setup and Hold Margin
MT41J64M16JT
DDR3-1333
AC150
VIHAC
900
VIHDC
850
VREF
750
VILDC
650
VILAC
600
tIS
190+75
tIH
140+50
EBD-To-Spice File Converter
•
•
•
•
EBD files can have branches to over 15 devices.
EBD files are generated automatically and sometimes have errors
that need to be checked and corrected.
Automatic tools from simulators that read EBD files automatically
cannot be trusted.
EBD-2-Spice file converter
– Creates RLC W-Elements for every section of etch
– Correctly identifies capacitors, resistors and inductors.
– Matches component names to device.ibs file and creates
package models automatically.
– Reduces what normally takes many hours into a few minutes.
EBD-To-Spice File Converter
EBD to Spice Converter
Get EBD File
Pin
Node 1
Pin 4
MT18JDF51272PDZ-1G4D1.ebd
4
10
Resistor Value
Pullup Voltage
120.0 ohm
3.30 v
Pin 4
Len=0.45044 L=3.54838e-009 C=1.07537e-012 R=0.038347 /
Len=0 R=15 /
Len=0.08552 L=3.54838e-009 C=1.07537e-012 R=0.038347 /
Len=0 C=1.06814e-014 /
Len=0.10000 L=1.38170e-009 C=3.66257e-013 /
Len=0 C=2.27241e-013 /
Len=0.39175 L=4.08327e-009 C=1.17171e-012 R=0.153375 /
Len=0 C=1.77130e-014 /
Fork
Len=0.10000 L=1.01349e-008 C=1.98847e-012 /
Len=0 C=1.06814e-014 /
Len=0.05459 L=3.54838e-009 C=1.07537e-012 R=0.038347 /
Node U20.B3
Endfork
Len=0.10000 L=1.38170e-009 C=3.66257e-013 /
Len=0 C=1.06814e-014 /
Len=0.05714 L=3.54838e-009 C=1.07537e-012 R=0.038347 /
Node U1.C7
.SUBCKT MODULE DIMM U20DIE U1DIE
$Pin 4
WElem1 N=1 10 0 11 0 RLGCFILE='.\Pin4\Pin4RLC1.rlc' L=0.45044
R2 11 12 15
WElem3 N=1 12 0 13 0 RLGCFILE='.\Pin4\Pin4RLC3.rlc' L=0.08552
C4 13 0 1.06814E-14
WElem5 N=1 13 0 14 0 RLGCFILE='.\Pin4\Pin4RLC5.rlc' L=0.1
C6 14 0 2.27241E-13
WElem7 N=1 14 0 15 0 RLGCFILE='.\Pin4\Pin4RLC7.rlc' L=0.39175
C8 15 0 1.7713E-14
$Fork 15
WElem10 N=1 15 0 16 0 RLGCFILE='.\Pin4\Pin4RLC10.rlc' L=0.1
C11 16 0 1.06814E-14
WElem12 N=1 16 0 17 0 RLGCFILE='.\Pin4\Pin4RLC12.rlc'
L=0.05459
WP_U20 N=1 17 0 U20DIE 0 RLGCFILE='.\Pin4\U20-B3.rlc' L=1
B_U20 nd_puU20 nd_pdU20 U20DIE node_out_of_inU20
file='v69a.ibs' model='DQ' typ=typ
$End Fork 15
WElem15 N=1 15 0 19 0 RLGCFILE='.\Pin4\Pin4RLC15.rlc' L=0.1
C16 19 0 1.06814E-14
WElem17 N=1 19 0 20 0 RLGCFILE='.\Pin4\Pin4RLC17.rlc'
L=0.05714
WP_U1 N=1 20 0 U1DIE 0 RLGCFILE='.\Pin4\U1-C7.rlc' L=1
B_U1 nd_puU1 nd_pdU1 U1DIE node_out_of_inU1 file='v69a.ibs'
model='DQ' typ=typ
.ENDS MODULE
Files Created